Semiconductor device and production method therefor

ABSTRACT

A semiconductor device having a high degree of reliability is provided. A second object of the invention is to provide a semiconductor device of high yield. The semiconductor includes a silicon substrate, a gate dielectric film formed on one main surface of the silicon substrate, a gate electrode formed by being stacked on the gate dielectric film and a diffusion layer containing arsenic and phosphorus. Both of the concentration of the highest concentration portion of arsenic and the concentration of the highest concentration portion of phosphorus are each at 10 26  atoms/m 3  or more and 10 27  atoms/m 3  or less, and the depth of the highest concentration portion of phosphorus from the surface of the silicon substrate is less than the depth of the highest concentration portion of arsenic.

TECHNICAL FIELD

The present invention relates to a semiconductor device having a highdegree of reliability.

BACKGROUND ART

In the steps of manufacturing a semiconductor device, it is necessary toimplant impurities into a silicon substrate and conduct a heat treatmentfor lowering electric resistance of the silicon substrate. In this case,crystal defects such as dislocations may sometimes occur in the siliconsubstrate. As a countermeasure for solving such a problem, a method ofimplanting arsenic of a large atomic radius and phosphorus of smallatomic radius together thereby decreasing strains more than in the caseof implanting only arsenic or phosphorus as described, for example, inJapanese Patent Laid-open Nos. 3-139827 and 3-184346.

However, as the structure has been complicated and microminiaturized andthe diffusion layer has become shallower, when dislocations or the likeoccur accompanying introduction of impurities, their effect on electriccharacteristics is increased.

In view of the above, it is an object of the present invention to solvethe foregoing subject and provide a semiconductor device having a highdegree of reliability and a manufacturing method of the semiconductordevice.

DISCLOSURE OF THE INVENTION

The present inventors have made earnest studies in order to obtain meanscapable of suppressing the effects caused by the occurrence of defectson electric characteristics and, as a result, have found that use of asemiconductor device or a manufacturing method thereof having thefollowing constitution is preferred for solving the subject of theinvention. Thus, a semiconductor device having a high degree ofreliability and a manufacturing method of the semiconductor device athigh yield are provided.

(1) A semiconductor device includes a semiconductor substrate, a gatedielectric film formed on one main surface of the silicon substrate, agate electrode formed by being stacked to the gate dielectric film, anddiffusion layer containing phosphorus as a first element and arsenic asa second element in which the depth from the surface of the siliconsubstrate where the concentration of the first element is highest isless than the depth from the surface of the silicon substrate where theconcentration of the second element is highest. The second element couldconceivably be antimony. An element heavier than the first element isselected as the second element. Further, it is preferred to select anelement having a diffusion coefficient larger than that of the firstelement as the second element. Further, one of the first element and thesecond element has a larger and the other has a smaller atomic radiusthan that of the main constituent element of the semiconductor substrate(for example, silicon in a silicon substrate).

A specific constitutional example includes a semiconductor substrate, aregion having impurities of an element belonging to the group III formedon one main surface of the semiconductor substrate, a gate dielectricfilm formed in the region, a gate electrode formed by being stacked onthe gate dielectric film, and a source or a drain containing impuritiesof an element belonging to the group V element corresponding to the gateelectrode, in which the source or the drain has a first elementbelonging to the group V and a second element belonging to the group V,one of the first element and the second element has a larger atomicradius and the other has a smaller atomic radius than that of the mainconstituent element of the semiconductor substrate, the depth from thesurface of the silicon substrate where the concentration of the firstelement is highest is less than the depth from the surface of thesilicon substrate where the concentration of the second element ishighest, and the first element is lighter than the second element.

Alternatively, it may be considered that the depth of a region where theconcentration of the first element is highest from the surface of thesilicon substrate is less than the depth of the region where theconcentration of the second element is 10²⁶ atoms/m³ or more from thesurface of the silicon substrate. Alternatively, it may also beconsidered that the depth of the region where the concentration of thefirst element is 10²⁶ atoms/m³ or more from the surface of the siliconsubstrate is less than the depth of a region where the concentration ofthe second element is 10²⁶ atoms/m³ or more from the surface of thesilicon substrate.

(2) Further, in addition to paragraph (1) described above, the depth ofthe highest concentration portion of the second element from the surfaceof the semiconductor substrate is 35 nm or less.

(3) Alternatively, in addition to paragraph (1) or (2) described above,both the concentration of the highest concentration portion of the firstelement and the concentration of the highest concentration of the secondelement are 10²⁶ atoms/m³ or more and 10²⁷ atoms/m³ or less. When ashallow diffusion layer region as in paragraph (2) is formed, it ispreferred to increase the concentration of impurities as high as from10²⁶ atoms/m³ to 10²⁷ atoms/m³ in order to lower the electricalresistance.

(4) Alternatively, in addition to at least one of paragraphs (1) to (3)described above, the implantation energy upon ion implantation ofphosphor as the first element is decreased to less than 0.45 times theimplantation energy upon ion implantation of arsenic as the secondelement. Further, the implantation energy upon ion implantation ofarsenic is 8×10⁻¹⁵ J or less. In a case where the second element isantimony, the implantation energy upon ion implantation of phosphorus isdecreased to less than 0.5 times the implantation energy upon ionimplantation of antimony. Further, the implanting energy upon ionimplantation of antimony is 7×10⁻¹⁵ J or less.

(5) Further, in addition to at least one of paragraph (1) to (4)described above, a step of implanting the first element after theimplantation of the second element is included.

(6) Further, in addition to at least one of paragraphs (1) to (5)described above, the width of the region having the second element inthe direction along the surface of the substrate is larger than thewidth of the region having the first element in the direction along thesurface of the substrate. The region can be defined, for example,substantially by the region having the first element or the secondelement. As an example, it may be considered to compare the width forthe region put between the high concentration region at the firstelement and the region put between the high concentration region of thesecond element in a region of a depth shallower than the highestconcentration depth of the first element. The depth can be consideredfor each individual device and, as an example, it may be considered toperform the comparison in the region at a depth of 5 nm from the surfaceof the substrate.

(7) Alternatively, a semiconductor device includes a semiconductorsubstrate, a p-well region having impurities of an element belonging tothe group III formed on one main surface of the semiconductor substrate,a gate dielectric film formed over the region, a gate electrode formedover the gate dielectric film, and a source or a drain containingimpurities of an element belonging to the group V formed correspondingto the gate electrode, in which the source or the drain has a firstelement belonging to the group V comprising phosphorus and a secondelement belonging to the group V comprising arsenic or antimony, a firstregion having the first element belonging to the group V is formed onthe cross section traversing the source or the drain, the second regionhaving the second element belonging to the group V is formed on theoutside of the first region, and the p-well region is formed on theoutside of the second region.

(8) Further, in paragraph (7) described above, the first region has thefirst element belonging to the group V at a concentration of 10²⁶atom/m³ or more and the second region has the second element belongingto the group V at a concentration of 10²⁶ atoms/m³ or more, and thep-well region is at a concentration of less than 10²⁶ atoms/m³.

(9) Further, in paragraph (7) described above, a region having the firstelement belonging to the group V at a concentration of less than 10²⁶atoms/m³ is present between the second region and the p-well region.

(10) A method of manufacturing a semiconductor device includes the stepsof forming a gate dielectric film in the p-well region, forming a gateelectrode, and forming a source or a drain, in which the step of formingthe source or the drain includes a second element introduction step ofusing the first element belonging to the group V comprising phosphorusand the second element belonging to the group V comprising arsenic orantimony, and a first element introduction step of introducing the firstelement after the second element introduction step to the substrate, andthe first element introduction step introduces the element by using themask used for the introduction of the second element.

(11) Alternatively, a method of manufacturing a semiconductor deviceincludes the steps of forming a gate dielectric film in the p-wellregion, forming a gate electrode and forming a source or a drain, andhas the steps of introducing the first element belonging to the group Vcomprising phosphorus to the substrate using the gate electrode as amask, depositing a dielectric film on the sidewall of the gateelectrode, a second element introduction step of introducing the secondelement belonging to the group V comprising arsenic or antimony to thesubstrate by using the dielectric film of the side wall as a mask and afirst element introduction step of introducing the first element afterthe second element introduction step to the substrate.

(12) A semiconductor device includes a plurality of transistor circuitseach including a p-well region, a gate dielectric film, a gateelectrode, and a source or a drain. The source or drain has a firstelement belonging to the group V comprising phosphorus and a secondelement belonging to the group V comprising arsenic or antimony.

In a first one of the transistor circuits, the gate electrode has afirst electrode formed over the gate dielectric film and a secondelectrode in connection with wiring by way of a dielectric layer overthe first electrode. The source or the drain has a first elementbelonging to the group V comprising phosphorus and a second elementbelonging to the group V comprising arsenic or antimony. A first regionhaving the first element belonging to the group V is formed on the crosssection traversing the source or drain, the second element belonging tothe group V is formed on the outside of the first region, and the p-wellregion is formed on the outside of second region. In addition, in asecond one of the second transistor circuits, the gate electrode has afirst electrode layer formed over the gate dielectric film and incommunication with the wiring, the source or the drain has a firstelement belonging to the group V comprising phosphorus and a secondelement belonging to the group V comprising arsenic or antimony. A firstregion having the first element belonging to the group V is formed onthe cross section traversing the source or drain, a second region havingthe second element belonging to the group V is formed to the outside ofthe first region, the p-well region is formed to the outside of secondregion, and a region having the first element belonging to the group Vis present between the second region and the p-well region.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1(a) through 1(e) are cross-sectional views for explaining asemiconductor device and a manufacturing method thereof according to afirst embodiment of the present invention;

FIG. 2 is a cross-sectional view for explaining a manufacturing methodtending to cause crystal defects;

FIG. 3 is a graph explaining the distribution of impurity concentrationtending to cause crystal defects;

FIG. 4 is a graph for explaining an example of an arsenic concentrationdistribution and a phosphorus concentration distribution causing lesscrystal defects in the invention;

FIG. 5 is a graph for explaining another example of an arsenicconcentration distribution and a phosphorus concentration distributioncausing less crystal defects in the invention;

FIG. 6 is a graph for explaining a comparative example of an arsenicconcentration distribution and a phosphorus concentration distribution;

FIG. 7 is a graph for explaining an example of an antimony concentrationdistribution and a phosphorus concentration distribution causing lesscrystal defects in the invention;

FIG. 8 is a graph for explaining another example of an antimonyconcentration distribution and a phosphorus concentration distributioncausing less crystal defects in the invention;

FIG. 9 is a view showing a relationship between an implanting energy anda depth of a highest concentration portion in the present invention;

FIGS. 10(a) through 10(e) are a cross sectional views for explaining asemiconductor device and a manufacturing method thereof according to asecond embodiment of the present invention;

FIG. 11 is a cross sectional view of a main portion of an SRAM as asemiconductor device according to a third embodiment of to theinvention;

FIG. 12 is a plan view of the main portion of the SRAM as asemiconductor device according to a third embodiment of the invention;

FIG. 13 is a cross sectional view of a main portion of a flash memory asa semiconductor device according to a fourth embodiment of theinvention; and

FIG. 14 is a plan view of the main portion of the flash memory as asemiconductor device according to the fourth embodiment of theinvention.

BEST MODE FOR CARRYING OUT THE INVENTION

Preferred embodiments of the present invention will be described indetail below.

At first, FIGS. 1(a) to 1(e) show a semiconductor device and amanufacturing method thereof according to a first embodiment of theinvention. In this embodiment, as shown in FIG. 1(a), a device isolationfilm 2, a gate dielectric film 3, a first gate electrode 4 and a secondgate electrode 5 are at first formed on a silicon substrate 1. In thedrawings, a p-type semiconductor or a p-well portion in which group IIIimpurities of an element belonging to the group III are diffused isshown in an enlarged scale.

Then, as shown in FIG. 1(b), impurities are ion implanted, for example,using the second gate electrode 5 as a mask to form diffusion layers 6and 7. Broken lines depicted in the portion of the diffusion layers 6and 7 show the highest concentration portion of the impurities. Further,in this embodiment, the diffusion layer 6 corresponds to a source and adiffusion layer 7 corresponds to a drain. Then, as a next step, a heattreatment, for example, at 800° C. or higher is conducted for making theatom arrangement in the diffusion layers 6 and 7 more orderly. Since aheat treatment is conducted also in the latter step in addition to theheat treatment described above, arsenic and antimony of large mass isused as the impurities of the diffusion layers 6 and 7. Further, with aview of diffusion coefficient, an element of smaller diffusioncoefficient is used. In a device having the gate with the lateral lengthof 130 nm or less, it is preferred that the impurity concentration inthe highest concentration portion of the diffusion layers 6 and 7 befrom 10²⁶ atoms/m³ to 10²⁷ atoms/m³ for keeping the electric resistancelow. Further, at a concentration more than 10²⁷ atoms/m³, since itbecomes difficult to easily suppress the occurrence of crystal defects,it is considered that the upper limit is 10²⁷ atoms/m³.

In the next step, as shown in FIG. 1(c), dielectric film side walls 8and 9 and a dielectric film 10 are deposited and, further, thedielectric film 10 is etched to form contact holes 11. Then, to lowerthe electrical resistance further, as shown in FIG. 1(d), impurities areion implanted to form diffusion layers 106 and 107. Subsequently, asshown in FIG. 1(e), plugs 12 are formed in the contact holes to form aninterconnection layer 13 for connection and a dielectric film 14. Tolower the contact resistance, a silicide film, for example, may beformed below the plugs 12. Further, although not illustrated, asuccessive step of forming a multi-layered interconnection for formingdielectric layer, plugs and an interconnection layer thereon may beapplied, or a barrier layer or a bonding layer may be formed in contactwith the interconnection layer or the plugs.

In FIGS. 1(d), and 1(e), solid lines shown for the portion of thediffusion layers 106 and 107 represent a highest concentration portionof the impurities. Subsequently, a heat treatment, for example, at 800°C. or higher is conducted to make arrangement of atoms in the diffusionlayers 106 and 107 more orderly. As described above, since the impurityconcentration of from 10²⁶ atoms/m³ to 10²⁷ atoms/m³ is necessary forthe highest concentration portion of the diffusion layers 6 and 7,crystal defects are liable to occur. Then, to suppress the occurrence ofthe crystal defects, use of phosphorus as the impurity for the diffusionlayers 106 and 107 is effective. This is because the mass is smallerthan arsenic or antimony used as the impurities for the diffusion layers6 and 7, or the diffusion coefficient is larger.

Further, since the atomic radius of arsenic or antimony used as theimpurity for the diffusion layers 6 and 7 is greater than that ofsilicon and compressive stress is generated, phosphorus with the atomicradius smaller than that of silicon is used for the diffusion layers 106and 107 in order to decrease the compressive stress. To attain theeffect of decreasing the stress, it is preferred that the concentrationfor the highest concentration portion of phosphorus is also at a highconcentration of from 10²⁶ atoms/m³ to 10²⁷ atoms/m³ like arsenic orantimony. Further, to suppress the occurrence of crystal defects, it isnecessary that the depth of the highest concentration portion ofphosphorus from the surface of the silicon substrate is less than thedepth for the highest concentration portion of arsenic. This is becausea large compressive stress is generated in the highest concentrationportion of arsenic or antimony and, when phosphorus at highconcentration passes through the portion, defects of dislocation thatare difficult to be eliminated by the heat treatment occurs by theenergy given upon passage (damages). Further, as the order ofimplantation, it is preferred to conduct a step of implanting phosphorusafter implantation of arsenic or antimony. This is shown in FIG. 2.Unlike FIG. 1(d), FIG. 2 shows that the solid line representing thehighest concentration portion of phosphorus in the diffusion layers 106and 107 is located below the broken line representing the highestconcentration portion of arsenic or antimony in the diffusion layers 6and 7 showing that phosphorus at a high concentration passed through thehighest concentration portion of arsenic or antimony. FIG. 2 showscrystal defects 206 and 207 referred to as dislocation caused by theenergy upon passage of phosphorus. In this case, the region in whichphosphorus is mainly diffused can be smaller than the region in whicharsenic or antimony is mainly diffused. Further, as the region where thedislocation occurs becomes shallower from the surface of the substrate,since it gives more significant effect on the electric characteristicsof a transistor compared with the case where the dislocation occurs in adeep region, it is important to adopt a countermeasure shown in thisembodiment.

FIG. 3 shows an example of molecular dynamical analysis for theconcentration distribution in a case of causing crystal defects as inthe case of FIG. 2. The depth for the highest concentration portion ofarsenic and phosphorus shown in FIG. 3 is a value in a case where theimplantation energy upon ion implantation of arsenic is at 6.4×10⁻¹⁵ Jand the implantation energy upon ion implantation of phosphorus is at4.8×10¹⁵ J. In this case, since the depth of the highest concentrationportion of phosphorus is deeper than the highest concentration portionof arsenic and phosphorus at a high concentration passes through thehighest concentration portion of arsenic to give damages, it is not easyto obtain an effect capable of suppressing crystal defects.

On the contrary, when the phosphorus implantation energy is decreased to2.88×10⁻¹⁵ J with the arsenic ion implantation energy kept at 6.4×10⁻¹⁵J as it is, the depths of the highest concentration portions can be madeequal to each other, as shown in FIG. 4. That is, in a case where thephosphorus implantation energy is controlled to 0.45 times the arsenicimplantation energy, the depths of the highest concentration portionscan be made equal to each other. In this case, it is possible tosuppress the phenomenon in which phosphorus at a high concentrationpasses through the highest concentration portion of arsenic to giveenergy (damages), thereby making it possible to suppress occurrence ofcrystal defects. Further, FIG. 5 shows a concentration distribution in acase where the phosphorus implantation energy is decreased to 0.38 timesthe arsenic implantation energy. In this case, the depth of the highestconcentration portion of phosphorus is shallower than the depth of thehighest concentration portion of arsenic. Accordingly, since it ispossible to prevent phosphorus with a high concentration from passingthrough the highest concentration portion of arsenic to give damages,occurrence of crystal defects can be suppressed. However, the phosphorusconcentrations may be less than 10²⁶ atoms/m³ even under the samerelation of implantation energy as that shown in FIG. 5. In this case,since it is difficult to obtain the effect of decreasing the compressivestress caused by arsenic of larger atomic radius with phosphorus ofsmaller atomic radius, crystal defects tend to occur when the heattreatment is undergone. FIG. 6 shows an example corresponding to such acase. In a case where the highest concentration of phosphorus is lessthan 10²⁶ atoms/m³ as shown in FIG. 6, phosphorus implantation cannotprovide the effect of suppressing the crystal defects and cannot providethe effect of lowering the electric resistance sufficiently.

FIG. 7 shows an example of using antimony instead of arsenic. FIG. 7shows a concentration distribution where the implantation energy uponion implantation of antimony is 5.6×10⁻¹⁵ J and the implantation energyupon phosphorus ion implantation is 2.8×10⁻¹⁵ J, and the depths of thehighest concentration portions are the same between antimony andphosphorus. That is, when the phosphorus implantation energy isdecreased to 0.5 times the antimony implantation energy, the depths ofthe highest concentration portions can be made equal to each other. Inthis case, it is possible to suppress the phenomenon in which phosphoruspasses through the highest concentration portion of antimony to givedamages thereto, thereby making it possible to suppress the occurrenceof crystal defects.

Further, FIG. 8 shows a concentration distribution in a case ofdecreasing the phosphorus implantation energy to 0.43 times the antimonyimplantation energy. In this case, since the depth of the highestconcentration portion of phosphorus is shallower than that of antimony,a phenomenon in which phosphorus with a high concentration passesthrough the highest concentration portion of antimony to give damagesthereto neither occurs. Accordingly, occurrence of crystal defects canbe suppressed. However, when the phosphorus implantation energy is mademore than 0.5 times the antimony implantation energy, since the depth ofthe highest concentration portion of phosphorus is deeper than that ofantimony, phosphorus at a high concentration passed through the highestconcentration portion of antimony to give damages thereto, so that it isdifficult to suppress the occurrence of the crystal defects.

Further, for the impurities, it is preferred to apply a step ofimplanting phosphorus after implantation of antimony.

For obtaining of the effect of suppressing the occurrence of the crystaldefects, it is preferred to control the depth of the highestconcentration portion of arsenic or antimony to 35 nm or less. Thecompressive stress generated by the intrusion of arsenic or antimonyhaving large atomic radius is larger as the depth of the highestconcentration portion increases. When it exceeds 35 nm, crystal defectsare caused at the stage before implantation of phosphorus. When thecrystal defects are generated in a shallow region, they give a moresignificant effect on electric characteristics compared with the casewhere the crystal defects are generated in a deep region. In particular,in a semiconductor device having such a thin diffusion layer that thehighest concentration portion of arsenic or antimony as an element to beimplanted deeply is 35 nm or less, it is effective in suppressing thedeterioration of electric characteristics by suppressing the formationof the crystal defects accompanying impurity introduction in thevicinity of the surface as described above. Further, it can be appliedmore effectively, for example, to a semiconductor device having such athin diffusion layer that the depth of the region where theconcentration of arsenic or antimony is highest is 25 nm or less.

In view of the relation between the implantation energy and the depth ofthe highest concentration portion obtained based on the analysis ofmolecular dynamics (FIG. 9), it is preferred that the arsenicimplantation energy is 8×10⁻¹⁵ J or less and the antimony implantationenergy is 7×10⁻¹⁵ J or less for restricting the depth of the highestconcentration portion to 35 nm or less.

Further, a step of implanting boron into a silicon substrate below thegate end may be applied after ion implantation for forming the diffusionlayers 6 and 7. Further, in a case where ion implantation at a lowconcentration (concentration lower than 10²⁶ atoms/m³) is conducted withan aim of changing the conduction type of the silicon substrate fromn-type to p-type or the like, it gives no influence on the desiredeffect. This is because such implantation gives no significant effect onthe profile near the highest concentration portion of the concentrationdistribution shown in FIGS. 3 to 7.

FIGS. 10(a) to 10(e) show a semiconductor device and a manufacturingmethod thereof according to a second embodiment of the presentinvention. This embodiment is different from the first embodiment mainlyin that the step of forming diffusion layers 106 and 107 is appliedbefore formation of dielectric film side walls 8 and 9. In this case,since the steps of forming the diffusion layers 6 and 7 and thediffusion layers 106 and 107 are continuous, the production steps aresimple.

FIG. 11 shows a cross-sectional view of a main portion of an SRAM(Static Random Access Memory) as a semiconductor device according to athird example of the invention. FIG. 11 is a cross sectional view takenalong line A-B of FIG. 2, which is a plan view for a main portion of theSRAM. The structure of this example is the same, for example, as thatshown in FIG. 2 and FIG. 3 of Japanese Patent Laid-open No. 10-79440,except the diffusion layers. Referring simply to the structure of thisembodiment with reference to FIG. 11, a p-type well 303 is formed on asilicon substrate 301 for instance, on which a gate dielectric film 307is formed. Gate electrodes 310 a, 310 b comprising, for example,polycrystal silicon are formed on the gate dielectric film 307 andphosphorus is ion implanted at such a low concentration (concentrationlower than 10²⁶ atoms/m³) as giving no significant effect on the profilein the vicinity of the highest concentration portion using the gateelectrodes as the mask, thereby forming diffusion layers 106 a, 107 a,and 188 a. Then, a dielectric film side wall 313 is formed and,subsequently, arsenic is implanted by using, for example, the gateelectrodes 310 a, 310 b and the dielectric film sidewall 313 as a mask,to form diffusion layers 6, 7, and 88. Then, a heat treatment, forexample, at 800° C. is applied and then phosphorus is ion implanted byusing quite the same portion as those described above as a mask, thatis, the gate electrodes 310 a, 310 b and the dielectric film sidewall313. In this case, the highest concentration and the implantation energyof arsenic and phosphorus forming the diffusion layers 67 and 88 and thediffusion layers 106 a, 107 a, 188 a, 106 b, 107 b, and 188 b are setwithin the range as described for the first embodiment having the effectof preventing crystal defects. Further, the effect can be obtained evenwhen any or all of the diffusion layers 106 a, 107 a and 188 a is notpresent. Further, the effect can also be obtained in a case where theheat treatment before formation of the diffusion layers 106 b, 107 b,and 108 b is not applied. Further, as described in the first embodiment,such a structure as using arsenic for the diffusion layers 106 a, 107 a,and 188 a, using phosphorus for the diffusion layers 6, 7 and 8 and notforming the diffusion layers 106 b, 107 b, and 108 may also be adopted.Also in this case, the highest concentration and the implantation energyof arsenic and phosphorus are determined within a range described forthe first embodiment having the effect of preventing crystal defects.After forming of the diffusion layers 106 b, 107 b, and 188 b, adielectric layers 315 is formed and contact plugs 322 and 337 are formedin contact holes 316 and 319, 328 formed in the layer. A multi-layeredinterconnection layer including interconnection layers L1, L2, 325, DL1and DL2, and dielectric layers 323 and 337 are formed over them.

With the constitution described above, since an effective shallowdiffusion layer can be formed in addition to the function and the effectexplained for the first example, the device can be miniaturized and theoperation speed of SRAM can be increased.

FIG. 13 shows a cross sectional view for a main portion of anon-volatile semiconductor memory device as a semiconductor device of afourth example according to the invention. FIG. 13 is a cross sectionalview taken along line A-B in FIG. 14, which is a plan view of a mainportion of a flash memory. Referring simply to the structure of thisexample with reference to FIG. 13, for example, a dielectric film 402comprising, for example, silicon oxide as a main constituent material isformed on a silicon substrate 401, over which electrodes 403, 404, and405 comprising, for example, polycrystal silicon as a main constituentmaterial is formed thereover. Then, a dielectric film 402, for example,comprising silicon oxide as a main constituent material, a dielectricfilm 407, for example, comprising silicon nitride as a main constituentmaterial and a dielectric film 408 comprising, for example, siliconoxide as a main constituent material are formed over them. Further, anelectrode 409 and word lines 410 and 411 comprising, for example,polycrystal silicon as a main constituent material are formed over them.Then, arsenic is ion implanted using the electrodes 409 and the worklines 410 and 411 as a mask to form diffusion layers 412, 413, and 414.Subsequently, phosphorus is implanted using quite identical portions asdescribed above as a mask, that is, the electrode 409, and the wordlines 410 and 411, to form diffusion layers 415, 416, and 417.

A dielectric film 418 comprising, for example, silicon oxide as a mainconstituent material is formed over them and, further, a bit line 419 isformed thereon. In this case, the highest concentration and implantationenergy of arsenic and phosphorus forming the diffusion layers 412, 413,and 414 and the diffusion layers 415, 416, and 417 are determined withinthe range described for the first embodiment having the effect ofpreventing the crystal defects. Further, as described for the firstembodiment, the diffusion layers 415, 416, and 417 may be formed afterformation of the dielectric film 418 and, in this case, the diffusionlayers 415, 416, and 417 are formed by using the electrode 409, the wordlines 410 and 411, and the dielectric film 418 as a mask.

In a state where plural electrodes are formed (with a dielectric layerbeing sandwiched between each of them) over a semiconductor substrate byway of an insulation layer as in a flash memory, it is considered thatthey are put under a complicate state of stress. However, thereliability of the device can be improved by preventing the occurrenceof defects (by forming them) while an element of larger atomic radiusand an element of smaller atomic radius than that of silicon of thesubstrate are used together, thereby suppressing the formation of thehighest concentration of the element implanted later passing through thehighest concentration region of the element implanted previously.

Further, in a semiconductor device having flash memories and logics suchas in a micro computer where flash memories are hybridized, it ispreferred to provide ion implantation steps separately in thelogic-constituting transistor such as applying a step of ion implantingphosphorus at low concentration (concentration lower than 10²⁶ atoms/m³)by using the gate electrode as the mask, subsequently implanting arsenicat a high concentration and then implanting phosphorus.

For the aid of understanding the drawings, main reference numerals areto be set forth.

1 . . . silicon substrate, 2 . . . device isolation film, 3 . . . gatedielectric film, 4 . . . first gate electrode, 5 . . . second gateelectrode, 6, 7 . . . diffusion layer, 7 a, 7 b . . . gate dielectricfilm, 8, 9 . . . dielectric film side wall, 10 . . . dielectric film, 11. . . contact hole, 12 . . . plug 13 . . . interconnection layer, 14 . .. dielectric layer, 106, 107 . . . diffusion layer, 206, 207 . . .dislocation, 88, 188 a, 188 b, 106 a, 106 b, 107 a, 107 b . . .diffusion layer, 301 . . . substrate, 303 . . . p-type well, 304 . . .n-type well, 305 . . . diffusion layer region, 306, 310 a, 310 b . . .gate electrode, 313 . . . dielectric film side wall, 315 . . .dielectric layer, 316, 319, 328 . . . contact hole, 322, 336 . . .contact plug, L1, L2, 325, DL1, DL2 . . . interconnection layer, DL1,323, 337 . . . dielectric layer, 401 . . . substrate, 402 . . .dielectric film, 403, 403, 405 . . . electrode, 406, 407, 408 . . .dielectric film, 409 . . . electrode, 410, 411 . . . word line, 412,413, 414, 415, 416, 417 . . . diffusion layer, 418 . . . dielectricfilm, 419 . . . bit line.

INDUSTRIAL APPLICABILITY

According to the present invention, a semiconductor device having a highdegree of reliability and a manufacturing method of the semiconductordevice can be provided.

1. A semiconductor device comprising: a semiconductor substrate; aregion having impurities of an element belonging to the group III formedon one main surface of the semiconductor substrate; a gate dielectricfilm formed in the region; a gate electrode formed by being stacked onthe gate dielectric film; and a source or a drain containing impuritiesof an element belonging to the group V element corresponding to the gateelectrode; wherein: the source or the drain has a first elementbelonging to the group V and a second element belonging to the group V;one of the first element and the second element is an element having anatomic radius larger than that of a main constituent elementconstituting the semiconductor substrate and the other is an elementhaving an atomic radius smaller than that of the main constituentelement; a depth from the surface of the silicon substrate where aconcentration of the first element is highest is less than a depth fromthe surface of the silicon substrate where the concentration of thesecond element is highest; and the first element is lighter than thesecond element.
 2. A semiconductor device according to claim 1, whereina width of a region having the second element in a direction along withthe substrate surface is larger than a width of a region having thefirst element in a direction along with the substrate surface.
 3. Asemiconductor device comprising: a silicon substrate; a region havingimpurities of an element belonging to the group III formed on one mainsurface of the semiconductor substrate; a gate dielectric film formed inthe region; a gate electrode formed by being stacked on the gatedielectric film; and a source or a drain containing impurities of anelement belonging to the group V element corresponding to the gateelectrode; wherein: the source or the drain has a first elementcomprising phosphorus and a second element comprising arsenic orantimony; a depth from the surface of the silicon substrate where aconcentration of the first element is highest is less than a depth fromthe surface of the silicon substrate where a concentration of the secondelement is highest; and a depth of the region where the concentration ofthe second element highest from the silicon substrate is 35 nm or less.4. A semiconductor device comprising: a silicon substrate; a regionhaving impurities of an element belonging to the group III formed on onemain surface of the semiconductor substrate; a gate dielectric filmformed in the region; a gate electrode formed by being stacked on thegate dielectric film; and a source or a drain containing impurities ofan element belonging to the group V element corresponding to the gateelectrode; wherein: the source or the drain has a first elementcomprising phosphorus and a second element comprising arsenic orantimony; a depth from the surface of the silicon substrate where aconcentration of the first element is highest is less than a depth fromthe surface of the silicon substrate where a concentration of the secondelement is highest; and a concentration of the element in the regionwhere the concentrations of the first element and the second element arehighest is from 10²⁶ atoms/m³ or more and 10²⁷ atoms/m³ or less.
 5. Asemiconductor device comprising: a silicon substrate; a P-well havingimpurities of an element belonging to the group III formed on one mainsurface of the silicon substrate; a gate dielectric film formed to theregion; a gate electrode formed by being stacked on the gate dielectricfilm; and a source or a drain containing impurities of an elementbelonging to the group V element corresponding to the gate electrode;wherein: at least the source or the drain is formed with a diffusionlayer containing a first element comprising phosphorus and a secondelement comprising at least arsenic or antimony; a depth from thesurface of the silicon substrate where a concentration of the firstelement is highest is less a the depth from the surface of the siliconsubstrate where the concentration of the second element is highest; thedepth of the region where the concentration of the second elementhighest from the silicon substrate is 35 nm or less; and theconcentration of the element in the region where the concentrations ofthe first element and the second element are highest is from 10²⁶atoms/m³ or more and 10²⁷ atoms/m³ or less.
 6. A semiconductor devicecomprising: a semiconductor substrate; a region having impurities of anelement belonging to the group III formed on one main surface of thesemiconductor substrate; a gate dielectric film formed to the region, agate electrode formed by being stacked to the gate dielectric film; anda source or a drain containing impurities of an element belonging to thegroup V element corresponding to the gate electrode; wherein: the sourceor the drain has a first element belonging to the group V and the secondelement belonging to the group V; one of the first element and thesecond element is an element having an atomic radius larger than that ofa main constituent element constituting the semiconductor substrate andthe other is an element having an atomic radius smaller than that of themain constituent element; a depth of the region where the concentrationof the first element is highest from the surface of the siliconsubstrate is less than a depth of the region where the concentration ofthe second element is 10²⁶ atoms/m³ or more from the surface of thesilicon substrate; and the first element is lighter than the secondelement.
 7. A semiconductor device comprising: a semiconductorsubstrate, a p-well region having impurities of an element belonging tothe group III formed on one main surface of the semiconductor substrate,a gate dielectric film formed over the region, a gate electrode formedover the gate dielectric film and a source or a drain containingimpurities of an element belonging to the group V formed correspondingto the gate electrode; wherein: the source or the drain has a firstelement belonging to the group V comprising phosphorus and a secondelement belonging to the group V comprising arsenic or antimony; and afirst region having the first element belonging to the group V is formedon a cross-section traversing the source or the drain, a second regionhaving the second element belonging to the group V is formed on theoutside of the first region, and the p-well region is formed on theoutside of the second region.
 8. A semiconductor device according toclaim 7, wherein the first region has the first element belonging to thegroup V at a concentration of 10²⁶ atoms/m³ or more, the second regionhas the second element belonging to the group V at a concentration of10²⁶ atoms/m³ or more, and the p-well region is at a concentration ofless than 10²⁶ atoms/m³.
 9. A semiconductor device according to claim 7,wherein a region having the first element belonging to the group V at aconcentration of less than 10²⁶ atoms/m³ is present between the secondregion and the p-well region.
 10. A semiconductor device including aplurality of transistor circuits each comprising: a semiconductorsubstrate; a p-well region having impurities of an element belonging tothe group III formed on one main surface of the semiconductor substrate;a gate dielectric film formed over the region; a gate electrode formedover the gate dielectric film; and a source or a drain containingimpurities of an element belonging to the group V formed correspondingto the gate electrode; wherein a first element belonging to the group Vcomprising phosphorus and a second element belonging to the group Vcomprising arsenic or antimony in the source or the drain; wherein, in afirst one of the transistor circuits, the gate electrode has a firstelectrode formed over the gate dielectric film and a second electrode inconnection with wiring by way of a dielectric layer over the firstelectrode, and the source or the drain has a first element belonging tothe group V comprising phosphorus and a second element belonging to thegroup V comprising arsenic or antimony, a first region having the firstelement belonging to the group V is formed on a cross-section traversingthe source or drain, a second region having the second element belongingto the group V is formed on the outside of the first region, and ap-well region is formed on the outside of second region; and wherein, ina second one of the second transistor circuits, the gate electrode has afirst electrode layer formed over the gate dielectric film and incommunication with the wirings the source or the drain has a firstelement belonging to the group V comprising phosphorus and a secondelement belonging to the group V comprising arsenic or antimony, a firstregion having the first element belonging to the group V is formed on across-section traversing the source or drain, a second region having thesecond element belonging to the group V is formed on the outside of thefirst region, and the p-well region is formed on the outside of secondregion, and a region having the first element belonging to the group Vis present between the second region and the p-well region.
 11. A methodof manufacturing a semiconductor device, comprising the steps of:forming a gate dielectric film on a silicon substrate in a region havingimpurities of an element belonging to the group III formed on one mainsurface of the silicon substrate; forming a gate electrode by stackingon the gate dielectric film; and forming a source or a drain containingimpurities of an element belonging to the group V corresponding to thegate electrode; wherein the step of forming the source or the drainincludes a forming step, using a first element belonging to the group Vand a second element belonging to the group V heavier than the firstelement, in which one of the first element and the second element is anelement having an atomic radius larger than that of the main constituentelement constituting the semiconductor substrate and the other is anelement having an atomic radius smaller than that of the mainconstituent element, and a depth where a concentration of the firstelement is highest from the surface of the silicon substrate is equal toor less than a depth where the concentration of the second element ishighest from the surface of the silicon substrate.
 12. A method ofmanufacturing a semiconductor device according to claim 11, wherein thedepth of the region where the concentration of the second element ishighest from the silicon substrate is 35 nm or less.
 13. A method ofmanufacturing a semiconductor device according to claim 11, wherein theconcentration in the region where the concentrations of the firstelement and the second element are highest is 10²⁶ atoms/m³ or more and10²⁷ atoms/m³ or less.
 14. A method of manufacturing a semiconductordevice according to claim 11, wherein in a case where the first elementis phosphorus and the second element is arsenic, implantation energyupon ion implantation of phosphorus is less than 0.45 times implantationenergy upon ion implantation of arsenic and, in a case where the secondelement is antimony, the implantation energy upon ion implantation ofphosphorus is less than 0.5 times the implantation energy upon ionimplantation of antimony.
 15. A method of manufacturing a semiconductordevice, comprising the steps of: forming on a silicon substrate a p-wellhaving impurities of an element belonging to the group III formed on onemain surface of the silicon substrate; forming a gate dielectric film inthe p-well; forming a gate electrode over the gate dielectric film; andforming a source or a drain containing impurities of an elementbelonging to the group v corresponding to the gate electrode; wherein atleast the step of forming the source or the drain includes a step ofusing a first element comprising phosphorus and a second elementcomprising at least arsenic or antimony and introducing the secondelement and a step of subsequently introducing the first element, adepth of the region where the concentration of the first element ishighest from the surface of the silicon substrate is less than a depthof the region where the concentration of the second element is highestfrom the surface of the silicon substrate, a region where theconcentration of the second element is highest is formed at a depth of35 nm or less from the silicon substrate, and the concentration of theelement in a region where the concentrations of the first element andthe second element are highest is 10²⁶ atoms/m³ or more and 10²⁷atoms/m³ or less.
 16. A method of manufacturing a semiconductor devicecomprising the steps of: forming a gate dielectric film on asemiconductor substrate in a p-well region having an impurity of anelement belonging to the group III formed on one main surface of thesemiconductor substrate; forming a gate electrode over the gatedielectric film, and forming a source or a drain containing an impurityof an element belonging to the group V corresponding to the gateelectrode; wherein the step of forming the source or the drain includesa second element introducing step of using first element belonging tothe group V comprising phosphorus and a second element of a groupbelonging to the group V comprising arsenic or antimony and introducingthe second element to the substrate, and a first element introductionstep of introducing the first element after the introduction of thesecond element introduction step to the substrate, and the first elementintroduction step introduces the first element using the mask used forthe introduction of the second element.
 17. A method of manufacturing asemiconductor device comprising the steps of: forming a gate dielectricfilm to a semiconductor substrate in a p-well region having an impurityof an element belonging to the group III formed on one main surface ofthe semiconductor substrate; forming a gate electrode over the gatedielectric film; forming a source or a drain containing impurities of anelement belonging to the group V corresponding to the gate electrode;introducing the first element belonging to the group V comprisingphosphorus to the substrate using the gate electrode as a mask;depositing a dielectric film on a sidewall of the gate electrode;introducing the second element belonging to the group V comprisingarsenic or antimony to the substrate by using the dielectric film on theside wall as a mask; and introducing the first element to the substrateafter the second element introduction step.